1. Field of the Invention
The present invention relates to a resin-sealed semiconductor device and a method of manufacturing the resin-sealed semiconductor device, and more particularly, to a resin-sealed semiconductor device in which lifted inner leads are provided in a sealing resin member and external connection terminals are provided on a bottom surface of the sealing resin member, and a method of manufacturing the resin-sealed semiconductor device.
2. Description of the Related Art
In recent years, a semiconductor element having an improved function and a reduced size is required to be mounted on a resin-sealed semiconductor device which is reduced in thickness and size. In addition, it is required to increase a die pad occupying area ratio to improve mounting efficiency (chip area/package occupying area) in semiconductor device board mounting, to thereby obtain a high semiconductor element mounting ratio. Further, a resin-sealed semiconductor device which may satisfy the demand for high heat radiation is required. Accordingly, the resin-sealed semiconductor device needs to have a new structure.
FIGS. 14A, 14B, and 14C show a structure of a conventional resin-sealed semiconductor device as an example. The resin-sealed semiconductor device includes: a semiconductor element 1; a die pad 2 supporting the semiconductor element 1; a bonding material 3 for bonding the semiconductor element 1 to the die pad 2; a plurality of inner leads 5 electrically connected to the semiconductor element 1 through bonding wires 4; and a sealing member 6 for sealing the semiconductor element 1, the die pad 2, the bonding material 3, the bonding wires 4, and the inner leads 5 with a sealing resin (see, for example, Japanese Patent Application Laid-open No. 2005-050948).
A resin package size of the conventional example of the resin-sealed semiconductor device has a length of approximately 1.2 mm in the X-axis direction, a length of approximately 1.6 mm in the Y-axis direction, and a length of approximately 0.48 mm in the Z-axis direction.
Both sides of a tip end of each of the inner leads are expanded as illustrated in FIGS. 14A, 14B, and 14C so as to secure bonding areas and to give sufficient lead-pull strength as anchors in a bending strength test for board mounting.
When a wire loop is to be formed by conventional wire bonding, as in a case of a wire loop 4d illustrated in FIG. 15, a large spacing L12 is required for avoiding electrical contact between the wire loop 4d and an end portion of the semiconductor element 1, and hence a predetermined height and a predetermined space are necessary.
With respect to a conventional die pad occupying area, (die pad area)/(resin package area) is 37% since a resin package area is 1.9 mm2 and a die pad area is 0.7 mm2.
In a case where each of length and breadth of the resin package is set not more than 1 mm, the following conventional problem occurs. When the conventional inner leads 5 are provided with a length equal to a length to an end surface of the die pad located in the sealing member 6, the area in which the die pad is provided becomes smaller, and hence the mounting efficiency, which is one of the package functions and is expressed as (chip area/package occupying area), reduces.
In order to solve the problem from the past, a semiconductor device in which a contained semiconductor element is tilted relative to the semiconductor device is disclosed (see, for example, Japanese Patent Application Laid-open No. 2008-103550).
However, it has been found that the conventional semiconductor device has new problems in terms of reductions in size and thickness and an increase in heat radiation. Hereinafter, the problems are specifically described.
A first problem is that, when the conventional inner lead shapes and the heights and spaces which are required for the wire loops formed by wire bonding are taken into account, it is difficult to form the inner leads and the wire loops in a small-size resin package, for example, in a region of which longitudinal and lateral lengths each are equal to or smaller than 0.8 mm. To be specific, there may be the following three factors.
A first factor is that the conventional inner lead shapes are required to secure the bonding areas and the lead-pull strength for serving as the anchors, and hence the inner leads require spaces, making it difficult to reduce the size.
In order to secure the bonding areas and the lead-pull strength for serving as the anchors a minimum necessary length and width are to be provided to the inner leads. When unnecessarily achieve the reduction in size, the bonding areas cannot be sufficiently secured, and hence the bonding may be unstable and reduced in reliability. When the portions saving as the anchors are too small, the portions do not serve as the anchors, and hence the strengths become insufficient.
A second factor is that the conventional layout requires securing the height of each of the wire loops in the wire bonding and a necessary spacing between the semiconductor element and a second bond position, and hence it is difficult to reduce the size because of the necessary height and the necessary spacing.
As illustrated in FIG. 15, when wire bonding is performed by a “downhill bonding” method of performing wire bonding while a position of a second bond 4b on a lead terminal surface is significantly lower than a position of a first bond 4a on a bonding pad of the semiconductor element 1, it is necessary to increase a loop height of the bonding wire (wire loop) 4d in order to prevent an easy electrical contact with the upper end portion of the semiconductor element 1 caused by an insufficient height of the wire loop. Accordingly, there is a disadvantage that it is necessary to thicken a resin thickness of the upper surface of the bonding pad of the semiconductor element 1. In addition, there is a disadvantage that, when a position shift amount of the semiconductor element 1 in a case of die bonding, a capillary diameter in a case of the second bond 4b, and a spacing for avoiding the electrical contact with the upper end portion of the semiconductor element 1 are taken into account, for example, the spacing L12 between the semiconductor device 1 and the second bond 4b increases.
A third factor is as follows. Since spacing between a bottom end portion of the die pad and an end portion of the external connection terminal becomes smaller with a reduction in size, in order to avoid a short circuit between board mounting wiring patterns during board mounting, it is necessary to secure a predetermined spacing between the bottom end portion of the die pad and the end portion of the external connection terminal. However, the securing of the predetermined spacing greatly hinders the reduction in size.
In an example of a quad flat no-lead (QFN) package, a lead spacing cannot be reduced because of constraint on etching due to corrosion removal and isotropy, and hence the spacing between the bottom end portion of the die pad and the end portion of the external connection terminal takes a large value. In an example of a package produced by electroforming, a large protrusion cannot be provided because of constraint on plating. When a small lead is formed, sufficient strength cannot be obtained to prevent separation from the sealing resin. This hinders the formation of the small lead. These examples of the QFN package and the package produced by electroforming show that such constraint causes an increase in size of the resin package and hinders the reduction in size.
A second problem is that it is more difficult to reduce the space necessary to provide the inner leads and the wire loops and to increase mounting efficiency (chip area/package occupying area) in mounting on the semiconductor device board of which a die pad occupying area ratio is not less than 30%.
When respective necessary functions are provided on the same area as in a conventional case without the reduction in size of the inner leads and the size of the resin package is reduced, the mounting area of the die pad reduces. Expansion of the mounting surface of the die pad for necessary length and width directly increases the package occupying area, degrading the mounting efficiency (chip area/package occupying area) in mounting on the semiconductor device board.
A third problem is that it is necessary to increase heat radiation efficiency of the semiconductor element of which a function is improved and a size is reduced.
Though in a conventional semiconductor device, generated heat from a semiconductor element transfers to a mounting pattern of a mounting board only through the external connection terminal in a case of a lifted die pad, a heat transfer distance between the semiconductor element and the mounting pattern of the mounting board also serving as a heat radiation portion for radiating heat to an outside of a sealing resin is long, and it is difficult to secure a contact area between the external connection terminal and the mounting pattern, with a result that generated heat from the semiconductor element cannot be efficiently radiated. Thus, generated heat from the semiconductor element is not sufficiently radiated, and hence there is a problem that the semiconductor element breaks because of thermal runaway, to thereby significantly reduce reliability. Even a semiconductor device of which a die pad is exposed from the bottom surface has the same problem in a case where the die pad is made of a low-heat conductivity material.